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/* Copyright (C) 2009-2021 Free Software Foundation, Inc. |
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|
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This file is part of GCC. |
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|
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GCC is free software; you can redistribute it and/or modify |
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it under the terms of the GNU General Public License as published by |
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the Free Software Foundation; either version 3, or (at your option) |
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any later version. |
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|
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GCC is distributed in the hope that it will be useful, |
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but WITHOUT ANY WARRANTY; without even the implied warranty of |
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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GNU General Public License for more details. |
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|
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Under Section 7 of GPL version 3, you are granted additional |
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permissions described in the GCC Runtime Library Exception, version |
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3.1, as published by the Free Software Foundation. |
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|
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You should have received a copy of the GNU General Public License and |
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a copy of the GCC Runtime Library Exception along with this program; |
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see the files COPYING3 and COPYING.RUNTIME respectively. If not, see |
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<http://www.gnu.org/licenses/>. */ |
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|
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#ifndef _X86GPRINTRIN_H_INCLUDED |
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# error "Never use <ia32intrin.h> directly; include <x86gprintrin.h> instead." |
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#endif |
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|
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/* 32bit bsf */ |
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extern __inline int |
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__attribute__((__gnu_inline__, __always_inline__, __artificial__)) |
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__bsfd (int __X) |
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{ |
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return __builtin_ctz (__X); |
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} |
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|
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/* 32bit bsr */ |
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extern __inline int |
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__attribute__((__gnu_inline__, __always_inline__, __artificial__)) |
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__bsrd (int __X) |
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{ |
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return __builtin_ia32_bsrsi (__X); |
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} |
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|
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/* 32bit bswap */ |
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extern __inline int |
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__attribute__((__gnu_inline__, __always_inline__, __artificial__)) |
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__bswapd (int __X) |
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{ |
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return __builtin_bswap32 (__X); |
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} |
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|
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#ifndef __iamcu__ |
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|
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#ifndef __SSE4_2__ |
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#pragma GCC push_options |
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#pragma GCC target("sse4.2") |
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#define __DISABLE_SSE4_2__ |
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#endif /* __SSE4_2__ */ |
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|
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/* 32bit accumulate CRC32 (polynomial 0x11EDC6F41) value. */ |
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extern __inline unsigned int |
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__attribute__((__gnu_inline__, __always_inline__, __artificial__)) |
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__crc32b (unsigned int __C, unsigned char __V) |
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{ |
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return __builtin_ia32_crc32qi (__C, __V); |
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} |
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|
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extern __inline unsigned int |
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__attribute__((__gnu_inline__, __always_inline__, __artificial__)) |
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__crc32w (unsigned int __C, unsigned short __V) |
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{ |
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return __builtin_ia32_crc32hi (__C, __V); |
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} |
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|
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extern __inline unsigned int |
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__attribute__((__gnu_inline__, __always_inline__, __artificial__)) |
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__crc32d (unsigned int __C, unsigned int __V) |
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{ |
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return __builtin_ia32_crc32si (__C, __V); |
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} |
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|
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#ifdef __DISABLE_SSE4_2__ |
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#undef __DISABLE_SSE4_2__ |
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#pragma GCC pop_options |
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#endif /* __DISABLE_SSE4_2__ */ |
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|
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#endif /* __iamcu__ */ |
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|
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/* 32bit popcnt */ |
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extern __inline int |
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__attribute__((__gnu_inline__, __always_inline__, __artificial__)) |
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__popcntd (unsigned int __X) |
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{ |
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return __builtin_popcount (__X); |
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} |
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|
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#ifndef __iamcu__ |
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|
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/* rdpmc */ |
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extern __inline unsigned long long |
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__attribute__((__gnu_inline__, __always_inline__, __artificial__)) |
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__rdpmc (int __S) |
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{ |
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return __builtin_ia32_rdpmc (__S); |
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} |
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|
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#endif /* __iamcu__ */ |
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|
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/* rdtsc */ |
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#define __rdtsc() __builtin_ia32_rdtsc () |
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|
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#ifndef __iamcu__ |
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|
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/* rdtscp */ |
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#define __rdtscp(a) __builtin_ia32_rdtscp (a) |
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|
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#endif /* __iamcu__ */ |
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|
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/* 8bit rol */ |
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extern __inline unsigned char |
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__attribute__((__gnu_inline__, __always_inline__, __artificial__)) |
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__rolb (unsigned char __X, int __C) |
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{ |
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return __builtin_ia32_rolqi (__X, __C); |
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} |
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|
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/* 16bit rol */ |
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extern __inline unsigned short |
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__attribute__((__gnu_inline__, __always_inline__, __artificial__)) |
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__rolw (unsigned short __X, int __C) |
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{ |
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return __builtin_ia32_rolhi (__X, __C); |
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} |
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|
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/* 32bit rol */ |
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extern __inline unsigned int |
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__attribute__((__gnu_inline__, __always_inline__, __artificial__)) |
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__rold (unsigned int __X, int __C) |
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{ |
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__C &= 31; |
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return (__X << __C) | (__X >> (-__C & 31)); |
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} |
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|
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/* 8bit ror */ |
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extern __inline unsigned char |
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__attribute__((__gnu_inline__, __always_inline__, __artificial__)) |
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__rorb (unsigned char __X, int __C) |
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{ |
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return __builtin_ia32_rorqi (__X, __C); |
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} |
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|
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/* 16bit ror */ |
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extern __inline unsigned short |
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__attribute__((__gnu_inline__, __always_inline__, __artificial__)) |
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__rorw (unsigned short __X, int __C) |
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{ |
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return __builtin_ia32_rorhi (__X, __C); |
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} |
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|
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/* 32bit ror */ |
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extern __inline unsigned int |
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__attribute__((__gnu_inline__, __always_inline__, __artificial__)) |
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__rord (unsigned int __X, int __C) |
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{ |
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__C &= 31; |
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return (__X >> __C) | (__X << (-__C & 31)); |
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} |
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|
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/* Pause */ |
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extern __inline void |
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__attribute__((__gnu_inline__, __always_inline__, __artificial__)) |
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__pause (void) |
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{ |
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__builtin_ia32_pause (); |
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} |
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|
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#ifdef __x86_64__ |
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/* 64bit bsf */ |
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extern __inline int |
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__attribute__((__gnu_inline__, __always_inline__, __artificial__)) |
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__bsfq (long long __X) |
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{ |
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return __builtin_ctzll (__X); |
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} |
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|
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/* 64bit bsr */ |
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extern __inline int |
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__attribute__((__gnu_inline__, __always_inline__, __artificial__)) |
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__bsrq (long long __X) |
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{ |
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return __builtin_ia32_bsrdi (__X); |
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} |
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|
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/* 64bit bswap */ |
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extern __inline long long |
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__attribute__((__gnu_inline__, __always_inline__, __artificial__)) |
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__bswapq (long long __X) |
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{ |
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return __builtin_bswap64 (__X); |
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} |
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|
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#ifndef __SSE4_2__ |
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#pragma GCC push_options |
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#pragma GCC target("sse4.2") |
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#define __DISABLE_SSE4_2__ |
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#endif /* __SSE4_2__ */ |
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|
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/* 64bit accumulate CRC32 (polynomial 0x11EDC6F41) value. */ |
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extern __inline unsigned long long |
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__attribute__((__gnu_inline__, __always_inline__, __artificial__)) |
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__crc32q (unsigned long long __C, unsigned long long __V) |
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{ |
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return __builtin_ia32_crc32di (__C, __V); |
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} |
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|
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#ifdef __DISABLE_SSE4_2__ |
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#undef __DISABLE_SSE4_2__ |
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#pragma GCC pop_options |
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#endif /* __DISABLE_SSE4_2__ */ |
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|
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/* 64bit popcnt */ |
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extern __inline long long |
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__attribute__((__gnu_inline__, __always_inline__, __artificial__)) |
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__popcntq (unsigned long long __X) |
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{ |
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return __builtin_popcountll (__X); |
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} |
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|
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/* 64bit rol */ |
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extern __inline unsigned long long |
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__attribute__((__gnu_inline__, __always_inline__, __artificial__)) |
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__rolq (unsigned long long __X, int __C) |
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{ |
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__C &= 63; |
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return (__X << __C) | (__X >> (-__C & 63)); |
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} |
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|
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/* 64bit ror */ |
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extern __inline unsigned long long |
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__attribute__((__gnu_inline__, __always_inline__, __artificial__)) |
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__rorq (unsigned long long __X, int __C) |
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{ |
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__C &= 63; |
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return (__X >> __C) | (__X << (-__C & 63)); |
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} |
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|
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/* Read flags register */ |
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extern __inline unsigned long long |
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__attribute__((__gnu_inline__, __always_inline__, __artificial__)) |
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__readeflags (void) |
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{ |
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return __builtin_ia32_readeflags_u64 (); |
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} |
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|
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/* Write flags register */ |
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extern __inline void |
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__attribute__((__gnu_inline__, __always_inline__, __artificial__)) |
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__writeeflags (unsigned long long __X) |
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{ |
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__builtin_ia32_writeeflags_u64 (__X); |
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} |
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|
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#define _bswap64(a) __bswapq(a) |
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#define _popcnt64(a) __popcntq(a) |
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#else |
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|
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/* Read flags register */ |
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extern __inline unsigned int |
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__attribute__((__gnu_inline__, __always_inline__, __artificial__)) |
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__readeflags (void) |
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{ |
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return __builtin_ia32_readeflags_u32 (); |
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} |
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|
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/* Write flags register */ |
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extern __inline void |
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__attribute__((__gnu_inline__, __always_inline__, __artificial__)) |
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__writeeflags (unsigned int __X) |
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{ |
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__builtin_ia32_writeeflags_u32 (__X); |
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} |
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|
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#endif |
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|
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/* On LP64 systems, longs are 64-bit. Use the appropriate rotate |
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* function. */ |
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#ifdef __LP64__ |
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#define _lrotl(a,b) __rolq((a), (b)) |
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#define _lrotr(a,b) __rorq((a), (b)) |
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#else |
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#define _lrotl(a,b) __rold((a), (b)) |
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#define _lrotr(a,b) __rord((a), (b)) |
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#endif |
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|
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#define _bit_scan_forward(a) __bsfd(a) |
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#define _bit_scan_reverse(a) __bsrd(a) |
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#define _bswap(a) __bswapd(a) |
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#define _popcnt32(a) __popcntd(a) |
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#ifndef __iamcu__ |
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#define _rdpmc(a) __rdpmc(a) |
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#define _rdtscp(a) __rdtscp(a) |
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#endif /* __iamcu__ */ |
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#define _rdtsc() __rdtsc() |
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#define _rotwl(a,b) __rolw((a), (b)) |
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#define _rotwr(a,b) __rorw((a), (b)) |
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#define _rotl(a,b) __rold((a), (b)) |
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#define _rotr(a,b) __rord((a), (b)) |
