| 1 |
/* |
| 2 |
* Copyright (C) 2007-2021 Free Software Foundation, Inc. |
| 3 |
* |
| 4 |
* This file is free software; you can redistribute it and/or modify it |
| 5 |
* under the terms of the GNU General Public License as published by the |
| 6 |
* Free Software Foundation; either version 3, or (at your option) any |
| 7 |
* later version. |
| 8 |
* |
| 9 |
* This file is distributed in the hope that it will be useful, but |
| 10 |
* WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 |
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 12 |
* General Public License for more details. |
| 13 |
* |
| 14 |
* Under Section 7 of GPL version 3, you are granted additional |
| 15 |
* permissions described in the GCC Runtime Library Exception, version |
| 16 |
* 3.1, as published by the Free Software Foundation. |
| 17 |
* |
| 18 |
* You should have received a copy of the GNU General Public License and |
| 19 |
* a copy of the GCC Runtime Library Exception along with this program; |
| 20 |
* see the files COPYING3 and COPYING.RUNTIME respectively. If not, see |
| 21 |
* <http://www.gnu.org/licenses/>. |
| 22 |
*/ |
| 23 |
|
| 24 |
#ifndef _CPUID_H_INCLUDED |
| 25 |
#define _CPUID_H_INCLUDED |
| 26 |
|
| 27 |
/* %eax */ |
| 28 |
#define bit_AVXVNNI (1 << 4) |
| 29 |
#define bit_AVX512BF16 (1 << 5) |
| 30 |
#define bit_HRESET (1 << 22) |
| 31 |
|
| 32 |
/* %ecx */ |
| 33 |
#define bit_SSE3 (1 << 0) |
| 34 |
#define bit_PCLMUL (1 << 1) |
| 35 |
#define bit_LZCNT (1 << 5) |
| 36 |
#define bit_SSSE3 (1 << 9) |
| 37 |
#define bit_FMA (1 << 12) |
| 38 |
#define bit_CMPXCHG16B (1 << 13) |
| 39 |
#define bit_SSE4_1 (1 << 19) |
| 40 |
#define bit_SSE4_2 (1 << 20) |
| 41 |
#define bit_MOVBE (1 << 22) |
| 42 |
#define bit_POPCNT (1 << 23) |
| 43 |
#define bit_AES (1 << 25) |
| 44 |
#define bit_XSAVE (1 << 26) |
| 45 |
#define bit_OSXSAVE (1 << 27) |
| 46 |
#define bit_AVX (1 << 28) |
| 47 |
#define bit_F16C (1 << 29) |
| 48 |
#define bit_RDRND (1 << 30) |
| 49 |
|
| 50 |
/* %edx */ |
| 51 |
#define bit_CMPXCHG8B (1 << 8) |
| 52 |
#define bit_CMOV (1 << 15) |
| 53 |
#define bit_MMX (1 << 23) |
| 54 |
#define bit_FXSAVE (1 << 24) |
| 55 |
#define bit_SSE (1 << 25) |
| 56 |
#define bit_SSE2 (1 << 26) |
| 57 |
|
| 58 |
/* Extended Features (%eax == 0x80000001) */ |
| 59 |
/* %ecx */ |
| 60 |
#define bit_LAHF_LM (1 << 0) |
| 61 |
#define bit_ABM (1 << 5) |
| 62 |
#define bit_SSE4a (1 << 6) |
| 63 |
#define bit_PRFCHW (1 << 8) |
| 64 |
#define bit_XOP (1 << 11) |
| 65 |
#define bit_LWP (1 << 15) |
| 66 |
#define bit_FMA4 (1 << 16) |
| 67 |
#define bit_TBM (1 << 21) |
| 68 |
#define bit_MWAITX (1 << 29) |
| 69 |
|
| 70 |
/* %edx */ |
| 71 |
#define bit_MMXEXT (1 << 22) |
| 72 |
#define bit_LM (1 << 29) |
| 73 |
#define bit_3DNOWP (1 << 30) |
| 74 |
#define bit_3DNOW (1u << 31) |
| 75 |
|
| 76 |
/* %ebx */ |
| 77 |
#define bit_CLZERO (1 << 0) |
| 78 |
#define bit_WBNOINVD (1 << 9) |
| 79 |
|
| 80 |
/* Extended Features (%eax == 7) */ |
| 81 |
/* %ebx */ |
| 82 |
#define bit_FSGSBASE (1 << 0) |
| 83 |
#define bit_SGX (1 << 2) |
| 84 |
#define bit_BMI (1 << 3) |
| 85 |
#define bit_HLE (1 << 4) |
| 86 |
#define bit_AVX2 (1 << 5) |
| 87 |
#define bit_BMI2 (1 << 8) |
| 88 |
#define bit_RTM (1 << 11) |
| 89 |
#define bit_MPX (1 << 14) |
| 90 |
#define bit_AVX512F (1 << 16) |
| 91 |
#define bit_AVX512DQ (1 << 17) |
| 92 |
#define bit_RDSEED (1 << 18) |
| 93 |
#define bit_ADX (1 << 19) |
| 94 |
#define bit_AVX512IFMA (1 << 21) |
| 95 |
#define bit_CLFLUSHOPT (1 << 23) |
| 96 |
#define bit_CLWB (1 << 24) |
| 97 |
#define bit_AVX512PF (1 << 26) |
| 98 |
#define bit_AVX512ER (1 << 27) |
| 99 |
#define bit_AVX512CD (1 << 28) |
| 100 |
#define bit_SHA (1 << 29) |
| 101 |
#define bit_AVX512BW (1 << 30) |
| 102 |
#define bit_AVX512VL (1u << 31) |
| 103 |
|
| 104 |
/* %ecx */ |
| 105 |
#define bit_PREFETCHWT1 (1 << 0) |
| 106 |
#define bit_AVX512VBMI (1 << 1) |
| 107 |
#define bit_PKU (1 << 3) |
| 108 |
#define bit_OSPKE (1 << 4) |
| 109 |
#define bit_WAITPKG (1 << 5) |
| 110 |
#define bit_AVX512VBMI2 (1 << 6) |
| 111 |
#define bit_SHSTK (1 << 7) |
| 112 |
#define bit_GFNI (1 << 8) |
| 113 |
#define bit_VAES (1 << 9) |
| 114 |
#define bit_AVX512VNNI (1 << 11) |
| 115 |
#define bit_VPCLMULQDQ (1 << 10) |
| 116 |
#define bit_AVX512BITALG (1 << 12) |
| 117 |
#define bit_AVX512VPOPCNTDQ (1 << 14) |
| 118 |
#define bit_RDPID (1 << 22) |
| 119 |
#define bit_MOVDIRI (1 << 27) |
| 120 |
#define bit_MOVDIR64B (1 << 28) |
| 121 |
#define bit_ENQCMD (1 << 29) |
| 122 |
#define bit_CLDEMOTE (1 << 25) |
| 123 |
#define bit_KL (1 << 23) |
| 124 |
|
| 125 |
/* %edx */ |
| 126 |
#define bit_AVX5124VNNIW (1 << 2) |
| 127 |
#define bit_AVX5124FMAPS (1 << 3) |
| 128 |
#define bit_AVX512VP2INTERSECT (1 << 8) |
| 129 |
#define bit_IBT (1 << 20) |
| 130 |
#define bit_UINTR (1 << 5) |
| 131 |
#define bit_PCONFIG (1 << 18) |
| 132 |
#define bit_SERIALIZE (1 << 14) |
| 133 |
#define bit_TSXLDTRK (1 << 16) |
| 134 |
#define bit_AMX_BF16 (1 << 22) |
| 135 |
#define bit_AMX_TILE (1 << 24) |
| 136 |
#define bit_AMX_INT8 (1 << 25) |
| 137 |
|
| 138 |
/* XFEATURE_ENABLED_MASK register bits (%eax == 0xd, %ecx == 0) */ |
| 139 |
#define bit_BNDREGS (1 << 3) |
| 140 |
#define bit_BNDCSR (1 << 4) |
| 141 |
|
| 142 |
/* Extended State Enumeration Sub-leaf (%eax == 0xd, %ecx == 1) */ |
| 143 |
#define bit_XSAVEOPT (1 << 0) |
| 144 |
#define bit_XSAVEC (1 << 1) |
| 145 |
#define bit_XSAVES (1 << 3) |
| 146 |
|
| 147 |
/* PT sub leaf (%eax == 0x14, %ecx == 0) */ |
| 148 |
/* %ebx */ |
| 149 |
#define bit_PTWRITE (1 << 4) |
| 150 |
|
| 151 |
/* Keylocker leaf (%eax == 0x19) */ |
| 152 |
/* %ebx */ |
| 153 |
#define bit_AESKLE ( 1<<0 ) |
| 154 |
#define bit_WIDEKL ( 1<<2 ) |
| 155 |
|
| 156 |
|
| 157 |
/* Signatures for different CPU implementations as returned in uses |
| 158 |
of cpuid with level 0. */ |
| 159 |
#define signature_AMD_ebx 0x68747541 |
| 160 |
#define signature_AMD_ecx 0x444d4163 |
| 161 |
#define signature_AMD_edx 0x69746e65 |
| 162 |
|
| 163 |
#define signature_CENTAUR_ebx 0x746e6543 |
| 164 |
#define signature_CENTAUR_ecx 0x736c7561 |
| 165 |
#define signature_CENTAUR_edx 0x48727561 |
| 166 |
|
| 167 |
#define signature_CYRIX_ebx 0x69727943 |
| 168 |
#define signature_CYRIX_ecx 0x64616574 |
| 169 |
#define signature_CYRIX_edx 0x736e4978 |
| 170 |
|
| 171 |
#define signature_INTEL_ebx 0x756e6547 |
| 172 |
#define signature_INTEL_ecx 0x6c65746e |
| 173 |
#define signature_INTEL_edx 0x49656e69 |
| 174 |
|
| 175 |
#define signature_TM1_ebx 0x6e617254 |
| 176 |
#define signature_TM1_ecx 0x55504361 |
| 177 |
#define signature_TM1_edx 0x74656d73 |
| 178 |
|
| 179 |
#define signature_TM2_ebx 0x756e6547 |
| 180 |
#define signature_TM2_ecx 0x3638784d |
| 181 |
#define signature_TM2_edx 0x54656e69 |
| 182 |
|
| 183 |
#define signature_NSC_ebx 0x646f6547 |
| 184 |
#define signature_NSC_ecx 0x43534e20 |
| 185 |
#define signature_NSC_edx 0x79622065 |
| 186 |
|
| 187 |
#define signature_NEXGEN_ebx 0x4778654e |
| 188 |
#define signature_NEXGEN_ecx 0x6e657669 |
| 189 |
#define signature_NEXGEN_edx 0x72446e65 |
| 190 |
|
| 191 |
#define signature_RISE_ebx 0x65736952 |
| 192 |
#define signature_RISE_ecx 0x65736952 |
| 193 |
#define signature_RISE_edx 0x65736952 |
| 194 |
|
| 195 |
#define signature_SIS_ebx 0x20536953 |
| 196 |
#define signature_SIS_ecx 0x20536953 |
| 197 |
#define signature_SIS_edx 0x20536953 |
| 198 |
|
| 199 |
#define signature_UMC_ebx 0x20434d55 |
| 200 |
#define signature_UMC_ecx 0x20434d55 |
| 201 |
#define signature_UMC_edx 0x20434d55 |
| 202 |
|
| 203 |
#define signature_VIA_ebx 0x20414956 |
| 204 |
#define signature_VIA_ecx 0x20414956 |
| 205 |
#define signature_VIA_edx 0x20414956 |
| 206 |
|
| 207 |
#define signature_VORTEX_ebx 0x74726f56 |
| 208 |
#define signature_VORTEX_ecx 0x436f5320 |
| 209 |
#define signature_VORTEX_edx 0x36387865 |
| 210 |
|
| 211 |
#ifndef __x86_64__ |
| 212 |
/* At least one cpu (Winchip 2) does not set %ebx and %ecx |
| 213 |
for cpuid leaf 1. Forcibly zero the two registers before |
| 214 |
calling cpuid as a precaution. */ |
| 215 |
#define __cpuid(level, a, b, c, d) \ |
| 216 |
do { \ |
| 217 |
if (__builtin_constant_p (level) && (level) != 1) \ |
| 218 |
__asm__ __volatile__ ("cpuid\n\t" \ |
| 219 |
: "=a" (a), "=b" (b), "=c" (c), "=d" (d) \ |
| 220 |
: "0" (level)); \ |
| 221 |
else \ |
| 222 |
__asm__ __volatile__ ("cpuid\n\t" \ |
| 223 |
: "=a" (a), "=b" (b), "=c" (c), "=d" (d) \ |
| 224 |
: "0" (level), "1" (0), "2" (0)); \ |
| 225 |
} while (0) |
| 226 |
#else |
| 227 |
#define __cpuid(level, a, b, c, d) \ |
| 228 |
__asm__ __volatile__ ("cpuid\n\t" \ |
| 229 |
: "=a" (a), "=b" (b), "=c" (c), "=d" (d) \ |
| 230 |
: "0" (level)) |
| 231 |
#endif |
| 232 |
|
| 233 |
#define __cpuid_count(level, count, a, b, c, d) \ |
| 234 |
__asm__ __volatile__ ("cpuid\n\t" \ |
| 235 |
: "=a" (a), "=b" (b), "=c" (c), "=d" (d) \ |
| 236 |
: "0" (level), "2" (count)) |
| 237 |
|
| 238 |
|
| 239 |
/* Return highest supported input value for cpuid instruction. ext can |
| 240 |
be either 0x0 or 0x80000000 to return highest supported value for |
| 241 |
basic or extended cpuid information. Function returns 0 if cpuid |
| 242 |
is not supported or whatever cpuid returns in eax register. If sig |
| 243 |
pointer is non-null, then first four bytes of the signature |
| 244 |
(as found in ebx register) are returned in location pointed by sig. */ |
| 245 |
|
| 246 |
static __inline unsigned int |
| 247 |
__get_cpuid_max (unsigned int __ext, unsigned int *__sig) |
| 248 |
{ |
| 249 |
unsigned int __eax, __ebx, __ecx, __edx; |
| 250 |
|
| 251 |
#ifndef __x86_64__ |
| 252 |
/* See if we can use cpuid. On AMD64 we always can. */ |
| 253 |
#if __GNUC__ >= 3 |
| 254 |
__asm__ ("pushf{l|d}\n\t" |
| 255 |
"pushf{l|d}\n\t" |
| 256 |
"pop{l}\t%0\n\t" |
| 257 |
"mov{l}\t{%0, %1|%1, %0}\n\t" |
| 258 |
"xor{l}\t{%2, %0|%0, %2}\n\t" |
| 259 |
"push{l}\t%0\n\t" |
| 260 |
"popf{l|d}\n\t" |
| 261 |
"pushf{l|d}\n\t" |
| 262 |
"pop{l}\t%0\n\t" |
| 263 |
"popf{l|d}\n\t" |
| 264 |
: "=&r" (__eax), "=&r" (__ebx) |
| 265 |
: "i" (0x00200000)); |
| 266 |
#else |
| 267 |
/* Host GCCs older than 3.0 weren't supporting Intel asm syntax |
| 268 |
nor alternatives in i386 code. */ |
| 269 |
__asm__ ("pushfl\n\t" |
| 270 |
"pushfl\n\t" |
| 271 |
"popl\t%0\n\t" |
| 272 |
"movl\t%0, %1\n\t" |
| 273 |
"xorl\t%2, %0\n\t" |
| 274 |
"pushl\t%0\n\t" |
| 275 |
"popfl\n\t" |
| 276 |
"pushfl\n\t" |
| 277 |
"popl\t%0\n\t" |
| 278 |
"popfl\n\t" |
| 279 |
: "=&r" (__eax), "=&r" (__ebx) |
| 280 |
: "i" (0x00200000)); |
| 281 |
#endif |
| 282 |
|
| 283 |
if (!((__eax ^ __ebx) & 0x00200000)) |
| 284 |
return 0; |
| 285 |
#endif |
| 286 |
|
| 287 |
/* Host supports cpuid. Return highest supported cpuid input value. */ |
| 288 |
__cpuid (__ext, __eax, __ebx, __ecx, __edx); |
| 289 |
|
| 290 |
if (__sig) |
| 291 |
*__sig = __ebx; |
| 292 |
|
| 293 |
return __eax; |
| 294 |
} |
| 295 |
|
| 296 |
/* Return cpuid data for requested cpuid leaf, as found in returned |
| 297 |
eax, ebx, ecx and edx registers. The function checks if cpuid is |
| 298 |
supported and returns 1 for valid cpuid information or 0 for |
| 299 |
unsupported cpuid leaf. All pointers are required to be non-null. */ |
| 300 |
|
| 301 |
static __inline int |
| 302 |
__get_cpuid (unsigned int __leaf, |
| 303 |
unsigned int *__eax, unsigned int *__ebx, |
| 304 |
unsigned int *__ecx, unsigned int *__edx) |
| 305 |
{ |
| 306 |
unsigned int __ext = __leaf & 0x80000000; |
| 307 |
unsigned int __maxlevel = __get_cpuid_max (__ext, 0); |
| 308 |
|
| 309 |
if (__maxlevel == 0 || __maxlevel < __leaf) |
| 310 |
return 0; |
| 311 |
|
| 312 |
__cpuid (__leaf, *__eax, *__ebx, *__ecx, *__edx); |
| 313 |
return 1; |
| 314 |
} |
| 315 |
|
| 316 |
/* Same as above, but sub-leaf can be specified. */ |
| 317 |
|
| 318 |
static __inline int |
| 319 |
__get_cpuid_count (unsigned int __leaf, unsigned int __subleaf, |
| 320 |
unsigned int *__eax, unsigned int *__ebx, |
| 321 |
unsigned int *__ecx, unsigned int *__edx) |
| 322 |
{ |
| 323 |
unsigned int __ext = __leaf & 0x80000000; |
| 324 |
unsigned int __maxlevel = __get_cpuid_max (__ext, 0); |
| 325 |
|
| 326 |
if (__maxlevel == 0 || __maxlevel < __leaf) |
| 327 |
return 0; |
| 328 |
|
| 329 |
__cpuid_count (__leaf, __subleaf, *__eax, *__ebx, *__ecx, *__edx); |
| 330 |
return 1; |
| 331 |
} |
| 332 |
|
| 333 |
static __inline void |
| 334 |
__cpuidex (int __cpuid_info[4], int __leaf, int __subleaf) |
| 335 |
{ |
| 336 |
__cpuid_count (__leaf, __subleaf, __cpuid_info[0], __cpuid_info[1], |
| 337 |
__cpuid_info[2], __cpuid_info[3]); |
| 338 |
} |
| 339 |
|
| 340 |
#endif /* _CPUID_H_INCLUDED */ |
